Automatic Test Equipment (ATE) 

Introduction

Within the intricate web of semiconductor production, there's a crucial yet often underestimated thread that weaves through every stage of semiconductor design, manufacturing, and packaging: semiconductor testing. Especially with the advent of higher-end and intricate chips, the reliance on testing becomes even more pronounced.

courtesy: Advantest V93000 EXA Scale™ SoC Test System solutions

Why testing is required?

Let's consider the journey of a wafer through the production flow as an illustration. Beginning as a bare wafer, it undergoes a series of critical processes including Wafer Preparation, Oxidation, Diffusion, Ion Implantation, Chemical-Vapour Deposition, Photolithography, Metallization, Packaging, and more. 

Defects can emerge at any stage, potentially accumulating as the process unfolds. Hence, it's imperative to ensure that the products meet stringent quality standards before advancing to subsequent steps like packaging and testing. 

Testing also plays a pivotal role in product classification, particularly notable in CPU manufacturing, where products are categorized based on comprehensive test results.

Wafer testing and final product testing predominantly rely on three types of equipment: Automated Test Equipment (ATE), sorting machines, and probe stations. Of these, ATE stands out as the cornerstone of testing equipment.

ATE testing methodology

The comprehensive chip production cycle encompasses chip design and validation, wafer fabrication, packaging, and testing stages. ATE primarily serves to discern chip functionality and defects throughout semiconductor manufacturing. 

ATE mainly serves 3 main purposes: 

1. Acceptance/rejection the chip-under-test (CUT)
2. Provides information on the fabrication process yield
3. Provides debug options in case of design weaknesses

the following 4 Basic Types of Testing are considered for an ATE:

Characterization testing:

This is also called design debug or verification testing, as it verifies correctness of design and test procedure. It is generally performed on new designs. Typically determines if design is correct and meets all of its specifications. Mainly AC, DC and functional tests performed.

The process is designed to 

• diagnose and correct errors, 
• set the final specifications and 
• is used to develop a production test program.

Production testing (go/no-go testing):

It is necessary that all of the fabricated chips must undergo a checking mechanism to ensure if it has some faulty outcomes. And hence factory testing of all manufactured chips is a must for parametric faults and for random defects. 

Enforces quality requirements by determining if chip specs are met.

The process here is shorter and less intensive than characteristic testing and it is performed on every chip. The main driving force is cost, so test time becomes most important parameter, test time must be minimized. However, the tests must have high coverage of modelled faults.

Burn-in or stress test: 

Burn-in testing is designed to stress the chip and accelerate the mechanisms that cause the chip to fail. The chip that pass production test might fail very quickly thereafter. Burn-in testing ensures reliability by forcing accelerated failures in these chips which have  passed production testing. The key here is to accelerate the failure mechanisms either by increasing temperature and/or voltage while applying test patterns.

Acceptance testing: 

sometimes customer performs tests on purchased parts to ensure its quality. Before incorporating manufactured chips into systems, system manufacturers perform some sort of characterization testing which is called an acceptance testing. Usually, this testing is carried out on a randomly selected chips among all incoming chips.

Components of an ATE Equipment

Let's briefly outline the composition of the CP test machine within the ATE toolset. It primarily comprises three main components:

Wafer test bench (Prober):

Throughout the testing phase, the wafer test bench utilizes the x and y coordinates of each DIE to construct an electronic wafer map. The test outcomes, whether pass or fail, are showcased on this map. This information is pivotal during the encapsulation process to identify and segregate the viable DIEs.

Wafer testing machine (Tester):

Tester is the Structure and Fundamental Control Principles of Wafer Testing Machine. The primary function of the wafer tester revolves around functional testing of the wafer. External control is administered through a workstation, facilitating the generation of essential input and reading signals such as voltage, current, and timing parameters crucial for the device under test. These signals are orchestrated through the test program definition, enabling the assessment of the device's quality

The probe card:

The probe card serves the crucial role of securely positioning the probe in direct contact with the wafer. It primarily comprises two components: the control card and the probe. Its principal function is to establish direct contact between the probe on the probe card and the pad or bump on the chip, enabling the extraction of the chip's signal. This, in turn, facilitates automatic measurement and reading of the chip's electrical signal through coordinated operation with peripheral test instruments and software control.

ATE Testing Procedure

When facing a batch of wafers for testing in an ATE machine, the undergone process unfolds as follows:

Step 1: Chip Differentiation

Chips are primed with various Test Mode functions, configuring pins to enter specified test states for diverse testing scenarios, including:

ATPG, which generates WGL or STIL format files for tester usage.

BIST (Built-In Self-Test) logic, capable of testing functionalities like ROM/RAM/Flash.

Function Test Mode, catering to specialized functional tests requiring additional hardware logic, such as ADC/DAC/clocks, etc.

Step 2: Selection of Test Facility and Model

Choosing an adept test facility and compatible test models is paramount. Considerations such as chip type, test specifications, content, and cost are weighed in the selection process.

Step 3: Probe Card and Test Program Development

The probe card, encompassing the probe and chip peripheral circuit, is crafted based on predetermined die coordinates and spacing information from chip design. Simultaneously, the test program, governing the entire testing process, is formulated. Engineers furnish files in formats like WGL/STIL/VCD, which are then tailored to the test machine's requirements and supplemented with additional test programs.

Step 4: Debugging and Result Analysis

Upon testing, the entire wafer's results yield a wafer map file and a logfile, such as an STD file. The wafer map delineates yield, test duration, error counts per BIN, and die locations, while the logfile furnishes specific test results. Engineers analyze this data to ascertain whether mass production readiness is achieved. During debugging, the test plan divides patterns (test vectors) into different BINs to pinpoint test error locations. Engineers then debug based on these error messages, iteratively refining patterns and test programs until all BINs pass scrutiny.

Step 5: Fine-Tuning and Process Optimization

As the process progresses towards mass production, leveraging statistical insights from multiple tests enables further refinement of the testing process. At this juncture, decisions regarding the retesting of faulty dies are made, with retesting often rectifying a portion of errors. It's crucial to monitor the stability of the yield rate; if it persists at a low level, testing may need to be paused for thorough data analysis, equipment checks, or discussions with the foundry. Upon achieving satisfactory outcomes, the transition to full-scale production ensues. During this phase, only the results of the CP test are passed on to the subsequent packaging facility for further processing.