An Introduction to DFT

Design for Manufactural Testability 

What is DFT?

Design for Testing (DFT) is a technique, which allows a design to become testable after production

Its uses some extra logic which we put in the normal design during the design process, that helps in determining if a fabricated design is having some manufactural defect or not

Why DFT is needed?

The process of manufacturing is not 100% error free

Due to small form factor of the device sometimes due to improper deposition of metals manufacturing defects happens

DFT helps to detect the manufactural defects and identify faulty devices typical Manufactural Defects

VLSI Fab process results in an interconnection of gates through metal layers & vias.

Manufactural defect occurs:

• When either the gates are not properly fabricated

• Defects in the metal interconnects

Typical stacking of layers in a Si chip

Typical Manufactural Defects:

• Gates are consist of typical CMOS designs

• Transistors in CMOS may conduct for all time or may not conduct at all due to imperfections

•  Leading to a Gate defect

• Metal interconnects for Gates may also have defects as follows:

• Unwanted joining or touching of metals traces

• Improper width of metal trace & in vias

Meal layers touching with each other

Unequal width due to manufacturing defect

Goals for DFT

Identify the manufactural defects

Controlled generation of input patterns which can detect a defect

Means to apply those input patterns selectively & to be able to observe the outputs for identification

Fast & robust pattern generation methods

DFT in design flow:

DFT in VLSI flow 

DFT Advantages & Disadvantages:

Advantages:

• Lets us to test a design efficiently in post fabrication stage

• Some DFT methods are useful in testing analog circuits as well

Disadvantages:

• DFT Techniques requires some extra area in the existing design

• Creates an area overhead, but unavoidable

Links to various chapters - 

1. DFT Stuck-at Faults
2. DFT Bridging Faults
3. DFT switch level faults
4. DFT Delay faults
5. DFT Scan Chain Insertion