DFT | Fault models | Stuck-at Faults

What is a fault model in DFT?

As Fabrication processes are erroneous, there are models to each type of manufacturing defects

Fault models allows us to generate appropriate bit patterns (some stimulus) which are used in Tester (during testing) after the design is fabricated

Acts as a guideline for the DFT analysis

Classification of Faults (Overall)

Manufacturing faults in a chip fabrication

Faults in gates

Transistors in gates shorted

Transistors in gates open & never conducts

Delays due to improper transition times at gate output

etc.

Faults in gate interconnect

Input or output of gates are shorted

Input or output of gates are connected to VDD or Ground

Imperfections in metal trace or via width

Faults and fault models

For each types of faults there exits fault models for properly describing the actual fault

For example, there exists a fault model which describes ‘touching of a net with ground’ called ‘Stuck-at-0’ fault, in this case the net is always retains the logical value 0, affecting the next logical gate operation as this net is always going to provide logic-0 input (never logic-1)

Hierarchy of Fault Models

DFT fault model table

Important fault models

Among all the faults models the following are extremely important & must to know models

– Stuck-at Fault models
– Delay Fault models
– Switch Level fault models

Here, stuck-at fault models are started, rest will be provided in next occurrences

Stuck-at Fault Models

It signifies a Model where a net is stuck to a constant value logical value (0 or 1), regardless of its driver

Two sub-cases exist:

stuck-at 1 (SA1), where Net is connected to VDD

stuck-at 0 (SA0), where Net is connected to GND

Stuck-at Fault Model, Example-1

Stuck-at Fault Model example

Patterns for SA faults, AND gate case

Red marked are the cases where there is a miss match w.r.t normal output

To identify a SA fault, the general idea is to apply reverse logic at the fault location, i.e., for Stuck-at-0 give 1 at the fault side, Stuck-at-1 give 0 at the fault side

patterns for stuck-at fault

SA fault, Procedure

To Check a SA fault, the general procedure:

Select a Fault

Apply the patterns & compare output if they are expected or not

For an unexpected response, a SA fault (for the given pattern) is present

Ex. In the previous AND gate to identify a Stuck-at-1 fault at A input we have to send pattern A=0, B=1 and for fault free circuit it should give Y=0, but for a SA1 fault, it will give 1

Exp-2, Find patterns for fault identification

SA fault pattern of 2:1 MUX

Stuck-at Fault general consideration

A total ‘2n’ numbers of SA faults can be there for ‘n’ net gate, here n = 3 (2 inputs A B, 1 output Y) so, total 6 SA faults can be possible, given only 1 net has a fault

A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values

The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k – 1

DFT Stuck-at Faults