DFT Bridging Faults

 DFT | Fault models | Bridging Faults

We have been dealing with different types of faults in out previous posts, it is now possible to get back and explore other fault models, in this post the faults associated with bridging of two nets is of interest, we’ll see why they are needed & ways to identify the faults 

Hierarchy and Abstraction in VLSI Design

Stuck-at, bridging of Fault Models & transitional delay models work on gate level representation of a

design

Hierarchy of different types of faults occurred in vlsi design

Bridging Faults in a Design

• Bridging faults appear when two or more normally distinct signal lines in a Boolean logic network are unintentionally shorted together

• Due to direct connection, a ‘wired logic’ is formed between them

Bridging Faults Cases

3 different cases might occur in bridging faults

Bridging faults occurrence 

Input Bridging

Both the inputs gets the same logical value

Input bridging fault

Output bridging

Bridging at the output of two or more gate fanout branch of a signal line is involved in a bridge

Example, fanout of two NOT gate under bridging

PMOS & NMOS here working as two resistors and the equivalent electrical circuit

looks like:

The table in the next should be used in case of a bridging fault (As per wire-OR or wire-AND)

The selection of wire-OR or AND depends on the usage of the logic family, for example, in CMOS circuits a bridging fault has to be replaced with a wire-AND model responses 

Feedback Bridging Fault Model

When an input is sorted with the output creating a feedback connection

Two cases can occur,

1. Latch creation, one of the output never changes

1. Sustained oscillation, constantly switches between logic 1 & 0 

Latch Creation

Oscillation

Bridging Fault Example

In the below figure there is a bridging fault between B & C, find out patterns to detect the said fault

Some important points on bridging faults:

• Not all Bridging faults is covered by SA patterns, it requires own patterns

• Bridging fault model changes with implemented logic families

• Number of bridging faults can be too many! in the order of O(n2), omega to the power 2; need to identify pairs of neighbouring signals from layout, called ‘fault extraction’ from layout