DFT switch level faults

 DFT | Fault models | Bridging Faults

So far we have considered faults at the gate level & entirely dealt with logical values at the output of a gate due to SA, bridging faults

But the transistors in a gate are also are equally susceptible to manufacturing defects like nets, transistors acts as switch in digital circuits and hence the name

Two possible cases can happen:

1. Transistor doesn’t turn on at all, called stuck-open fault
2. Transistor is on always, called stuck-on fault

Stuck-open Faults

This happens when one or more transistors doesn’t conduct, here let’s assume TBP doesn’t conduct

Stuck-short Faults

This happens when one or more transistors always conduct 

Form a conducting path between VDD and GND in static state, just like a voltage divider arrangement between them

Output logic values depends on relative impedance of transistors, and hence NOT detected by Boolean testing at the output

Stuck-on fault can be detected by IDDQ testing, i.e., Drain to source quiescent current measurement

IDDQ testing 

Some important points on switch level faults:

• Stuck-off fault requires 2 sets of patterns where SA required 1for a single fault

• Stuck-on fault is detected by IDDQ testing, but in lower technology nodes, detecting current change is challenging