DFT | Fault models | Delay Faults
Stuck-at, bridging & switching faults are a kind of a fault in which a manufacturing defect resulted in a functional error, thus the responses of an input pattern are incorrect; but there are a class of faults which doesn’t generate a functional error, but due to some delay, the right responses doesn’t arrive at the output of a circuit; in this section the faults associated with delays are of interest, we’ll see why they are coming into picture & ways to identify delay faults
What is a Delay fault?
- Due to a certain delay, introduced in a data path, appropriate logical values are not received at an observation point within a specified time, a delay fault is occurred
- A delay fault is not a functional fault, it is just due to some manufacturing defect, the right value doesn’t reach within the right time, but the value will be correct after some delay which is greater than the specified time
Delay fault example
Sources of Delay fault in Gates
Delay can occur due to propagation of data through a gate (tpd) or delay in data transition (tR) at output
• In the CMOS diagram CL represents an equivalent load capacitance seen by AND gate, consisting of
{ gate to Drain capacitance, drain to bulk capacitance, etc.}
Any manufacturing defect that affects the value of CL also changes the charging & discharging time constant, thus affecting the transition time of the gate
A delay fault model is considered when a gate takes too much time to stabilize an output, hence a problem of data synchronization occurs, called a transitional delay fault
Transitional Delay fault Model
- Slow-to-rise: While a transition from 0 to 1 the gate too much time that within a certain time response doesn’t stabilize to logic 1
- Slow-to-fall: While a transition from 1 to 0 the gate too much time that within a certain time response doesn’t stabilize to logic 1
Sources of Delay fault in Nets
The path delay is more about the time the data spend in the wire, from a gate to another
Due to improper manufacturing the following situation can occur, and results in an increase in RC delay in path:
- Random defects: Resistive opens, resistive bridging
- Systematic defects: crosstalk, stray capacitance building between lines
Detection of delay faults
So we have two delay faults to deal with
- Transitional Delay Fault (TDF)
- Path Delay Fault (PDF)
Locally Delay faults are detected with the help of ‘Delay Testing’
Delay faults needs two-patterns as opposed to one-pattern test for stuck-at faults
Delay Testing
A Delay testing consists of a pair of test patterns (test vectors):
- V1: initialize circuit state
- V2: launch transition, propagate fault effect to output
One has to precisely control T in such a way that it is the deciding factor
Delay Testing Example
Delay Testing Summary
- Delay Faults are not functional faults, they are just not able to produce response at rated clock speed but able to produce appropriate results at slower clocks
- We have seen that a Delay Testing requires two set of vectors unlike Stuck-at faults
- In a delay testing a control time T is very important parameter in which the selection of test clock and functional clock is dependent
- There are 2 categories of Delay Fault TDF & PDF