DFT Techniques | Scan Chain Insertion
We have been introduced to DFT, where it was shown that due to some manufacturing defects a functionally simulated correct design may not behave well after fabrication, we also have seen stuck-at fault model that described a type of faults where a net is stuck with logic 0/1, with some examples the patterns were created to identify certain SA faults; now it is essential to know how the patterns are applied selectively & observe the responses from the faulty nets, several techniques are used to do this, easiest one is ‘scan insertion’, once the concept of scan insertion is understood, understanding the other fault models, along with their pattern generation & pattern application would be easier, after scan insertion the regular flow of other fault models will be continued
Controllability Of a design
It means the ability to selectively apply inputs to a design, to set up appropriate logic value (0/1) at desired location of circuit
In a typical design, the only place where we can provide input is the input interface of the design, it is difficult to directly provide inputs to the gates which are sitting deep down the logic
Observability Of a design
It means the ability to observe the response of a given controlled inputs to a design, to set up appropriate logic value (0/1) at desired location of circuit
In a typical design, the only place where we can observe the output is the output interface of the design
For a node to be tested, it should be controllable as well as observable. The nodes closer to the input can be controllable, but not observable easily since they are passed through a layer of FFs and combinational circuit,
While the nodes after the FFs can be observable since they are closer to output, but aren’t controllable directly
Of course, some of these nodes can be controllable and observable if we find a technique to initialize the flip-flops to the desired value
Let’s partition this circuit into three different parts, the red, blue & yellow parts can be combined to represent a part of a bigger combinational circuit & every sequential circuit can be represented in this way
• The inputs to the combinational circuit from the flip flops (FFs) are called as pseudo-primary inputs, while the outputs of the combinational circuit to FFs are called pseudo-primary outputs
The idea is to separate the flip-flops from the rest of the circuit so that the combinational part can be tested easily using appropriate patterns
• If we can control and observe these pseudo inputs and outputs to the combinational circuit, we can easily test this circuit
• But how to control or observe these pseudo-primary inputs or pseudo-primary outputs? For this, we need to replace the standard flip-flops with a special type of flip-flop through which we can initialize and control from outside the design
Scanned Flipflop
MUXed-D Scan Flip Flop: This is a conventional flip-flop with a 2:1 MUX before it.
Scan Flip-Flop has four main pins:
- Scan Chain: Scan In (SI), Scan Out (SO).
- Logic: Data In (DI), Data Out (DO).
Scan Enable pin = the select line to the multiplexer,
Selects between the Data In and the Scan In input,
The DFF captures the value, which is decided by the Scan Enable pin. Scan Flip-Flop has two functions:
Shift data from SI pin to SO pin (when SE = 1)
Capture data from the combinational circuit (when SE =0)
Scan chain Insertion
In the modified design, the scan flip-flops are stitched together one after another in a Scan Chain, the process is called ‘Scan Chain Insertion’
Now, we have the choice to either connect the combinational circuit output to the flip flop inputs or to connect it to Scan In pin
Depending on Scan Enable, we can have two working mode:
- Normal mode, when SE = 0, FF will get Di
- Test Mode, when SE= 1, FF will get Si
Normal Mode
In normal mode, Scan Flip-Flops are configured to perform capture operation
They capture the response from the logic and then apply the response to the logic in the next clock cycle
The Normal Mode is activated when Scan Enable is logic-o
The flip-flops capture the data from pseudo-primary outputs of the combinational logic
This mode is exactly similar to the original mode, and the Scan flip-flops can be simply ignored in this case in lieu of normal flip-flops
Test Mode
In test mode, the scan flip-flops are first configured to perform shift operation so we can shift-in our test pattern.
And then the scan flip-flops are configured to capture the response from the logic.
Finally, we configure the flip-flops to perform the shift-out operation so that we can observe the values in the Scan flip-flops.
The following steps are involved in test mode:
- Step 1: Shift In
- Step 2: Capture
- Step 3: Shift Out
Example of scan chain Insertion
Application of patten to detect a SA fault at the shown net using scan insertion
A SA fault at the input net of an OR gate requires a logic-1 input at the fault location at G2
Which is the output of G1, hence in =1 , also the output of FF2 has to be 1 in test mode
The test vector is {in, Q1, Q2} = {1, 0,1}
Steps 1 (Shift In):
SE = 1 (Test Mode), through Sin {1,0} will be serially shifted in 2 clock pulses,
in doing so values {Q1, Q2} = { 1, 0} will be available,
also a primary input in = 1 can be given & the response is then available at o/p of G2
Steps 2 (Capture):
SE = 0 (Normal Mode), apply 1 clock pulse in functional mode,
in doing so, values {FF1, FF2} = { D, 1} will be available, D is the defective value
Steps 3 (Shift out):
SE = 1 (Test Mode), apply 1 clock pulse, Sout becomes {1, D},
check D and compare with fault free response and take decision about the given SA0 fault
Note: In Test mode the clock used is different than the Normal mode
Scan chain Insertion Summary
- Scan chain Insertion provides use the controllability to apply a fault pattern selectively & observability to check the response
- Scan chain Insertion is a process in which normal FF are replaced with Scanned FF & stitched together so that serially patterns can be applied throughout the design
- It is done when the netlist of a design is available
- Typical tools for scan chain insertions are, Synopsys – DFT Compiler, Siemens - Tessent
- The clock used in test mode is usually slow w.r.t functional clocks, typically 10-40 MHz