Pattern Generation
In DFT, a manufacturing defect, whether it is due to Stuck-at, bridging, switching, or delay faults, the only way to find out is to apply certain test patterns as per the type of fault it is; we have seen that these patterns can be transferred into fault site through a scan chaining flops and is the most widely used & cheap method of achieving DFT; but we have derived the patterns with the help of truth table so far and this is not the way how the patterns are generated practically; in this section, we’ll try to look at different ways to generate patterns with pros & cons associated with it.
What is Pattern Generation (PG)?
- The aim of test generation at the gate level is to verify that each logic gate in the circuit is functioning correctly, and the interconnections are good
- We apply a specific set of signals to the circuit input as a test to identify a certain fault as per fault model considered for example, a SA 0/1 at a certain node or a delay in a gate etc. this is known as the Test Vector,
- To detect all the stuck-at faults, we need to apply a series of test vectors sequentially, this series is also known as the Test Pattern, here our task is to generate patterns
Pattern Generation problems
- The simplest way to test these designs is by verifying the responses to all input combinations, this can be done by applying each input combination and observing each corresponding output, called exhaustive testing
- Here, for n input signals one has to consider 2n no of single SA faults & path delay faults, 3^K-1 numbers of multiple SA faults etc. as discussed previously, this means there are huge no of set of test vectors or test patterns are associated with
- What would happen there are millions of gates in a design?
- The number of test vectors would grow drastically, With a clock frequency of100 MHz, a tester would take probably 300 ms & 130 days!! for a 25 & 50 input designs respectively
- Also, have to store all 250 Golden or reference responses for the comparisons with responses from the faulty design, memory requirement increases exponentially with no of states to compare
- A tester is a device where designs are tested after fabrication, it is a clock speed & memory constrained device , ex. Agilent 93000 SOC Series tester has a 1024 Pins Test-head
Pros & cons of Truth Table approach
• The most straightforward method for generating tests for a particular fault is to compare the truth-table of the fault-free and the faulty circuits
• It is less time consuming than ‘exhaustive testing’, where for n inputs one has to apply 2n input patterns
• But a kind of manual approach to match the response form faulty design, not suitable for automatic generation of patterns
Other Pattern Generation Methods
All though TT method is straight forward it is not suitable for when no of tests are very large, there are slightly improved approaches:
- Boolean Difference Method
- Path Sensitization Method
Boolean Difference Method
Boolean Difference Example
Boolean Difference Pros & cons
- Boolean difference takes much lesser time as compared to Exhaustive testing & even with Truth Table based approach
- It is a Mathematics based approach can be implemented using software's, and hence reduces human efforts to generate patterns
- At the last step we have to find out input combinations, that satisfy Fgood ⊕ Ffaulty = 1 relation, suitable algorithm has to be find out for this purpose, sometimes it is complex
Path Sensitization Method
The key point in Boolean Difference is one has to know the ‘Logical Expression’ of the given circuit, F = f (A,B,C,....)
But in practical cases such opportunities are not available, in fact after synthesis DFT activity starts with the ‘netlist’, which is just an interconnection of logic gates but no information of ‘Logical Expression’
So, in practical cases this method can’t be used, rather a family of PG methods is based on Path Sensitization Method which as advantages over previous methods
Path Sensitization Method has 3 basic steps which doesn’t require any logical expression of a given circuit, the steps are:
- Fault excitation
- Forward Propagation
- Backward Propagation
let’s try to understand the method with an example;
Step-1: Fault excitation
It is the step where a Fault is introduced at the fault site by forcing the net by an opposite value signal to which it is stuck-at,
Step -2: Forward Propagation
The effect of forcing is propagated till the primary output where the resultant logical value is observed
Step-3: Backward Propagation
Once the path has been sensitized successfully, we just need to traverse behind every gate and assign the desired value to the net until we reach the primary inputs
Path Sensitization pros & cons
- The main advantage of Path Sensitization is it doesn’t require any Logical Expression, so it can readily be applicable to netlist
- Also very fast as compared to TT & Boolean difference method, as there is no of solving difference equations like in Boolean difference
- But, here at the 3rd stage we need sophisticated backward propagation algorithm and sometimes it becomes complex